`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:16:33 07/22/2011 
// Design Name: 
// Module Name:    counter 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module counter( clock, direction,  count_out);
    input clock;
    input direction;
    output [3:0] count_out;
    
   reg [3:0] count_int=0;
   
		always @(posedge clock)
      if (direction)
         count_int <= count_int + 1;
      else
         count_int <= count_int - 1;
assign count_out= count_int;
endmodule


						